HC705E5GRSSLASHD datasheet(100/148 Pages) NXP

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Synchronous Serial Interface (SSI)

General Release Specification

MC68HC705E5 — Rev. 1.0

Synchronous Serial Interface (SSI)

12.4 SSI Registers

The SSI registers are described in the following subsections.

12.4.1 SSI Control Register

This register is located at address $000A. A reset clears all of these bits,

except bit 3 which is set. Writes to this register during a transfer should

be avoided, with the exception of clearing the SE bit to disable the SSI.

In addition, the clock polarity, rate, data format, and master/slave

selection should not be changed while the SSI is enabled (SE = 1) or

being enabled. Always disable the SSI, by clearing the SE bit, before

altering control bits within the SCR.

SIE — SSI Interrupt Enable

This bit determines whether an interrupt request should be generated

when a transfer is complete. Reset clears this bit.

1 = An interrupt request will be made if the CPU is in the run or wait

mode of operation and the status flag bit SF is set.

0 = No interrupt requests will be made by the SSI.

SE — SSI Enable

When this bit is set, it enables the SSI and SCK pins. When this bit is

cleared, any transmission in progress is aborted and the SCK and

SDIO are three-stated. The SE bit is readable and writable any time.

Clearing SE while a data transfer is occurring will abort the

transmission and reset the bit counter. Reset clears this bit.

1 = Enable the SSI module.

0 = Disable the SSI module.

Address:

$000A

Bit 7

654321

Bit 0

Read:

SIE

LSBF

MSTR

CPOL

SDIR

SR1

SR0

Write:

Reset:

00001000

Figure 12-4. SSI Control Register (SCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 100 Page - NXP Semiconductors

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