HC705E5GRSSLASHD datasheet(99/148 Pages) NXP

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Synchronous Serial Interface (SSI)

SSI Signals

MC68HC705E5 — Rev. 1.0

General Release Specification

Synchronous Serial Interface (SSI)

pin will depend on the value of the CPOL bit. Data can be sent or

received in either MSB first format (LSBF = 0) or LSB first format

(LSBF = 1).

If (CPOL = 1), the first falling edge of SCK will shift the first data bit

out to the SDIO pin. Subsequent falling edges of SCK will shift the

remaining data bits out.

If (CPOL = 0), the first data bit will be driven out to the SDIO pin before

the first rising edge of SCK. Subsequent falling edges of SCK will shift

the remaining data bits out.

SDIO as an Input Pin

The SDIO pin will accept data once the SSI is enabled and the SDIR

bit = 0. Valid data must be present at least 100 ns before the rising

edge of the clock and remain valid for 100 ns after the edge. See

Figure 12-2 and Figure 12-3.

Figure 12-2. Synchronous Serial Interface Timing (CPOL = 1)

Figure 12-3. Synchronous Serial Interface Timing (CPOL = 0)

SDIO

BIT 1

BIT 2

BIT 3

BIT 7

SCK

BIT 8

SDIO

BIT 1

BIT 2

BIT 3

BIT 7

SCK

BIT 8

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 99 Page - NXP Semiconductors