HC705E5GRSSLASHD datasheet(44/148 Pages) NXP

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Resets

General Release Specification

MC68HC705E5 — Rev. 1.0

Resets

The RESET pin can also act as an open-drain output. It will be pulled to

a low state by an internal pulldown that is activated by any reset source.

This RESET pulldown device will be asserted only by three to four cycles

of the internal clock, PH2 (PH2 period = E clock period), or as long as an

internal reset source is asserted. When the external RESET pin is

asserted, the pulldown device will be turned on for the three to four

internal clock cycles only.

5.4 Internal Resets

The four internally generated resets are the initial power-on reset

function, the COP watchdog timer reset, the illegal address detector, and

the disabled STOP instruction. The only reset sources that can alter the

MCU’s operating mode are termination of the external RESET input or

the internal COP watchdog timer. The other internal resets will not have

any effect on the mode of operation when their reset state ends. All

internal resets will also assert (pull to logic 0) the external RESET pin for

the duration of the reset or three to four internal clock cycles, whichever

is longer.

5.5 Power-On Reset (POR)

The internal POR is generated on power-up to allow the clock oscillator

to stabilize. The POR is strictly for power turn-on conditions and is not

able to detect a drop in the power supply voltage (brown-out). There is

an oscillator stabilization delay of 4064 internal processor clock cycles

after the oscillator becomes active.

The POR will generate the RST signal which will reset the CPU. If any

other reset function is active at the end of the 4064-cycle delay, the RST

signal will remain in the reset condition until the other reset condition(s)

end.

POR will activate the RESET pin pulldown device connected to the pin.

VDD must drop below VPOR for the internal POR circuit to detect the next

rise of VDD.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 44 Page - NXP Semiconductors