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HC705E5GRS/D Datasheet(PDF) 78 Page - NXP Semiconductors |
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HC705E5GRS/D Datasheet(HTML) 78 Page - NXP Semiconductors |
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78 / 148 page  Motorola Bus (M Bus) Interface General Release Specification MC68HC705E5 — Rev. 1.0 Motorola Bus (M Bus) Interface 11.6 M-Bus Registers Five different registers are used in the M-bus interface. The internal configuration of these registers is discussed in the following paragraphs. NOTE: The register addresses show only the low-order address bits (for example ABL3–ABL0). The registers can be placed anywhere in the device memory map by generating an appropriate module select signal in the map logic. A block diagram of the M-bus system is shown in Figure 11-3. 11.6.1 M-Bus Address Register Bit 1–Bit 7 Each of these bits contains its own specific slave address. This register is cleared upon reset. Address: $0018 Bit 7 654321 Bit 0 Read: MAD7 MAD6 MAD5 MAD4 MAD3 MAD2 MAD1 Write: Reset: 0000000 — = Unimplemented Figure 11-3. M-Bus Address Register (MADR) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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