HC705E5GRSSLASHD datasheet(85/148 Pages) NXP

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Motorola Bus (M Bus) Interface

M-Bus Registers

MC68HC705E5 — Rev. 1.0

General Release Specification

Motorola Bus (M Bus) Interface

MAL — Arbitration Lost Bit

MAL is set by hardware when the arbitration procedure is lost during

a master transmission. This bit must be cleared by software.

SRW — R/W Command Bit

When MAAS is set, the R/W command bit of the calling address (sent

from master) is latched into the R/W command bit (SRW). Checking

this bit, the CPU can select the slave transmit/receive mode

according to the command of master.

1 = Slave transmit, master reading from slave

0 = Slave receive, master writing to slave

MIF — M-Bus Interrupt Bit

MIF is set when an interrupt is pending. This will cause an M-bus

interrupt request provided MIEN is set. This bit is set when one of the

following events occurs:

–

Transmission of one byte is completed. The bit is set at the

falling edge of the ninth clock.

–

Reception of a calling address which matches its own specific

address in slave receive mode.

–

Arbitration is lost.

This bit must be cleared by writing a logic 0 to it.

RXAK — Receive Acknowledge Bit

If RXAK is low, it indicates an acknowledge signal has been received

after the completion of an 8-bit data transmission on the bus. If RXAK

is high, it means no acknowledge signal is detected at the ninth clock.

1 = No acknowledge received

0 = Acknowledge received

RXAK is set upon reset.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 85 Page - NXP Semiconductors