TUSB7340 datasheet(110/122 Pages) TI2

110 / 122 page

Table 8-196. MSI-X Table and PBA Register Map (continued)

OFFSET

Entry 4 Message Address

0040h

Entry 4 Message Upper Address

0044h

Entry 4 Message Data

0048h

Entry 4 Vector Control

004Ch

Entry 5 Message Address

0050h

Entry 5 Message Upper Address

0054h

Entry 5 Message Data

0058h

Entry 5 Vector Control

005Ch

Entry 6 Message Address

0060h

Entry 6 Message Upper Address

0064h

Entry 6 Message Data

0068h

Entry 6 Vector Control

006Ch

Entry 7 Message Address

0070h

Entry 7 Message Upper Address

0074h

Entry 7 Message Data

0078h

Entry 7 Vector Control

007Ch

Reserved

0080h-0FFFh

Pending Bits 7 through 0

1000h

Reserved

1001h-1FFFh

Refer to the PCI Local Bus Specification, Revision 3.0 for descriptions of these registers.

TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

www.ti.com

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