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EP4CE40 Datasheet(PDF) 49 Page - Altera Corporation |
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EP4CE40 Datasheet(HTML) 49 Page - Altera Corporation |
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49 / 488 page  Chapter 3: Memory Blocks in Cyclone IV Devices 3–13 Memory Modes November 2011 Altera Corporation Cyclone IV Device Handbook, Volume 1 Figure 3–12 shows the Cyclone IV devices M9K memory block in shift register mode. ROM Mode Cyclone IV devices M9K memory blocks support ROM mode. A .mif initializes the ROM contents of these blocks. The address lines of the ROM are registered. The outputs can be registered or unregistered. The ROM read operation is identical to the read operation in the single-port RAM configuration. FIFO Buffer Mode Cyclone IV devices M9K memory blocks support single-clock or dual-clock FIFO buffers. Dual clock FIFO buffers are useful when transferring data from one clock domain to another clock domain. Cyclone IV devices M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer. f For more information about FIFO buffers, refer to the Single- and Dual-Clock FIFO Megafunction User Guide. Figure 3–12. Cyclone IV Devices Shift Register Mode Configuration W w × m × n Shift Register m-Bit Shift Register m-Bit Shift Register m-Bit Shift Register m-Bit Shift Register W W W W W W W n Number of Taps |
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