EP4CE40 datasheet(42/488 Pages) ALTERA

42 / 488 page

3–6

Chapter 3: Memory Blocks in Cyclone IV Devices

Overview

Cyclone IV Device Handbook,

November 2011

Altera Corporation

Volume 1

Figure 3–3 and Figure 3–4 show the address clock enable waveform during read and

write cycles, respectively.

Mixed-Width Support

M9K memory blocks support mixed data widths. When using simple dual-port, true

dual-port, or FIFO modes, mixed width support allows you to read and write

different data widths to an M9K memory block. For more information about the

different widths supported per memory mode, refer to “Memory Modes” on

page 3–7.

Figure 3–3. Cyclone IV Devices Address Clock Enable During Read Cycle Waveform

Figure 3–4. Cyclone IV Devices Address Clock Enable During Write Cycle Waveform

inclock

rden

rdaddress

q (synch)

q (asynch)

latched address

(inside memory)

dout0

dout1

dout4

dout1

dout4

dout5

addressstall

doutn-1

dout1

doutn

dout1

dout0

dout1

inclock

wren

wraddress

latched address

(inside memory)

addressstall

data

contents at a0

contents at a1

contents at a2

contents at a3

contents at a4

contents at a5

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