EP4CE40 datasheet(85/488 Pages) ALTERA

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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices

5–23

Clock Feedback Modes

October 2012

Altera Corporation

Cyclone IV Device Handbook,

Volume 1

Clock Feedback Modes

Cyclone IV PLLs support up to five different clock feedback modes. Each mode

allows clock multiplication and division, phase shifting, and programmable duty

cycle. For the supported feedback modes, refer to Table 5–5 on page 5–18 for

Cyclone IV GX PLLs and Table 5–6 on page 5–19 for Cyclone IV E PLLs.

1 Input and output delays are fully compensated by the PLL only if you are using the

dedicated clock input pins associated with a given PLL as the clock sources.

When driving the PLL using the GCLK network, the input and output delays may not

be fully compensated in the Quartus II software.

Source-Synchronous Mode

If the data and clock arrive at the same time at the input pins, the phase relationship

between the data and clock remains the same at the data and clock ports of any I/O

element input register.

Figure 5–12 shows an example waveform of the data and clock in this mode. Use this

mode for source-synchronous data transfers. Data and clock signals at the I/O

element experience similar buffer delays as long as the same I/O standard is used.

Source-synchronous mode compensates for delay of the clock network used,

including any difference in the delay between the following two paths:

■

Data pin to I/O element register input

■

Clock input pin to the PLL phase frequency detector (PFD) input

1 Set the input pin to the register delay chain in the I/O element to zero in the

Quartus II software for all data pins clocked by a source-synchronous mode PLL.

Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II

software.

Figure 5–12. Phase Relationship Between Data and Clock in Source

-Synchronous Mode

Data pin

PLL reference

clock at input pin

Data at register

Clock at register

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