EP4CE40 datasheet(76/488 Pages) ALTERA

76 / 488 page

5–14

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices

Clock Networks

Cyclone IV Device Handbook,

October 2012

Altera Corporation

Volume 1

The inputs to the clock control blocks on each side of the Cyclone IV GX device must

be chosen from among the following clock sources:

■

Four clock input pins

■

Ten PLL counter outputs (five from each adjacent PLLs)

■

Two, four, or six DPCLK pins from the top, bottom, and right sides of the device

■

Five signals from internal logic

Figure 5–4. Clock Networks and Clock Control Block Locations in Cyclone IV E Devices

Notes to Figure 5–4:

(1) There are five clock control blocks on each side.

(2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. You can use the other CDPCLK pins as

general-purpose I/O (GPIO) pins.

(3) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated.

(4) PLL_3 and PLL_4 are not available in EP4CE6 and EP4CE10 devices.

PLL_1

PLL_4

PLL_2

PLL_3

(2)

CDPCLK7

CDPCLK0

CDPCLK1

DPCLK1

DPCLK[11.10]

DPCLK[9..8]

CLK[11..8]

CDPCLK6

DPCLK0

CLK[3..1]

GCLK[19..0]

CDPCLK5

DPCLK7

CLK[7..4]

DPCLK6

CDPCLK4

CDPCLK2

DPCLK[3..2]

CLK[15..12]

DPCLK[5..4]

CDPCLK3

(3)

(4)

(3)

Clock

Control

Block (1)

Clock

Control

Block (1)

Clock

Control

Block (1)

Clock

Control

Block (1)

EP4CE40 Datasheet(PDF) 76 Page - Altera Corporation

EP4CE40 Datasheet(HTML) 76 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL