EP4CE40 datasheet(24/488 Pages) ALTERA

24 / 488 page

1–10

Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Architecture

Cyclone IV Device Handbook,

April 2014

Altera Corporation

Volume 1

f For more information, refer to the External Memory Interfaces in Cyclone IV Devices

chapter.

Configuration

Cyclone IV devices use SRAM cells to store configuration data. Configuration data is

downloaded to the Cyclone IV device each time the device powers up. Low-cost

configuration options include the Altera EPCS family serial flash devices and

commodity parallel flash configuration options. These options provide the flexibility

for general-purpose applications and the ability to meet specific configuration and

wake-up time requirements of the applications.

Table 1–9 lists which configuration schemes are supported by Cyclone IV devices.

IEEE 1149.6 (AC JTAG) is supported on all transceiver I/O pins. All other pins

support IEEE 1149.1 (JTAG) for boundary scan testing.

f For more information, refer to the JTAG Boundary-Scan Testing for Cyclone IV Devices

chapter.

For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you

must use passive serial (PS) configuration mode for the EP4CGX15/22/30 devices

and use fast passive parallel (FPP) configuration mode for the EP4CGX30F484 and

EP4CGX50/75/110/150 devices.

f For more information, refer to the Configuration and Remote System Upgrades in

Cyclone IV Devices chapter.

The cyclical redundancy check (CRC) error detection feature during user mode is

supported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is only

supported for the devices with the core voltage of 1.2 V.

f For more information about CRC error detection, refer to the SEU Mitigation in

Cyclone IV Devices chapter.

High-Speed Transceivers (Cyclone IV GX Devices Only)

Cyclone IV GX devices contain up to eight full duplex high-speed transceivers that

can operate independently. These blocks support multiple industry-standard

communication protocols, as well as Basic mode, which you can use to implement

your own proprietary protocols. Each transceiver channel has its own pre-emphasis

and equalization circuitry, which you can set at compile time to optimize signal

integrity and reduce bit error rates. Transceiver blocks also support dynamic

reconfiguration, allowing you to change data rates and protocols on-the-fly.

Table 1–9. Configuration Schemes for Cyclone IV Device Family

Devices

Supported Configuration Scheme

Cyclone IV GX

AS, PS, JTAG, and FPP (1)

Cyclone IV E

AS, AP, PS, FPP, and JTAG

Note to Table 1–9:

(1) The FPP configuration scheme is only supported by the EP4CGX30F484 and EP4CGX50/75/110/150 devices.

EP4CE40 Datasheet(PDF) 24 Page - Altera Corporation

EP4CE40 Datasheet(HTML) 24 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL