EP4CE40 datasheet(34/488 Pages) ALTERA

34 / 488 page

2–6

Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices

LAB Control Signals

Cyclone IV Device Handbook,

November 2009

Altera Corporation

Volume 1

LAB Interconnects

The LAB local interconnect is driven by column and row interconnects and LE

outputs in the same LAB. Neighboring LABs, phase-locked loops (PLLs), M9K RAM

blocks, and embedded multipliers from the left and right can also drive the local

interconnect of a LAB through the direct link connection. The direct link connection

feature minimizes the use of row and column interconnects, providing higher

performance and flexibility. Each LE can drive up to 48 LEs through fast local and

direct link interconnects.

Figure 2–5 shows the direct link connection.

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs. The control

signals include:

■

Two clocks

■

Two clock enables

■

Two asynchronous clears

■

One synchronous clear

■

One synchronous load

You can use up to eight control signals at a time. Register packing and synchronous

load cannot be used simultaneously.

Each LAB can have up to four non-global control signals. You can use additional LAB

control signals as long as they are global signals.

Synchronous clear and load signals are useful for implementing counters and other

functions. The synchronous clear and synchronous load signals are LAB-wide signals

that affect all registers in the LAB.

Figure 2–5. Cyclone IV Device Direct Link Connection

LAB

Direct link

interconnect

to right

Direct link interconnect from

right LAB, M9K memory

block, embedded multiplier,

PLL, or IOE output

Direct link interconnect from

left LAB, M9K memory

block, embedded multiplier,

PLL, or IOE output

Local

Interconnect

Direct link

interconnect

to left

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