EP4CE40 datasheet(40/488 Pages) ALTERA

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3–4

Chapter 3: Memory Blocks in Cyclone IV Devices

Overview

Cyclone IV Device Handbook,

November 2011

Altera Corporation

Volume 1

Figure 3–1 shows how the wren and byteena signals control the RAM operations.

When a byteena bit is deasserted during a write cycle, the old data in the memory

appears in the corresponding data-byte output. When a byteena bit is asserted during

a write cycle, the corresponding data-byte output depends on the setting chosen in

the Quartus® II software. The setting can either be the newly written data or the old

data at that location.

1 Byte enables are only supported for True Dual-Port memory configurations when

both the PortA and PortB data widths of the individual M9K memory blocks are

multiples of 8 or 9 bits.

Packed Mode Support

Cyclone IV devices M9K memory blocks support packed mode. You can implement

two single-port memory blocks in a single block under the following conditions:

■

Each of the two independent block sizes is less than or equal to half of the M9K

block size. The maximum data width for each independent block is 18 bits wide.

■

Each of the single-port memory blocks is configured in single-clock mode. For

more information about packed mode support, refer to “Single-Port Mode” on

page 3–8 and “Single-Clock Mode” on page 3–15.

Figure 3–1. Cyclone IV Devices byteena Functional Waveform

(1)

Note to Figure 3–1:

(1) For this functional waveform, New Data mode is selected.

inclock

wren

address

data

q (asynch)

XXXX

doutn

ABFF

FFCD

ABCD

ABFF

FFCD

ABCD

byteena

XXXX

ABCD

FFFF

ABFF

FFCD

contents at a0

contents at a1

contents at a2

rden

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