EP4CE40 datasheet(96/488 Pages) ALTERA

96 / 488 page

5–34

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices

PLL Reconfiguration

Cyclone IV Device Handbook,

October 2012

Altera Corporation

Volume 1

PLL Reconfiguration

PLLs use several divide counters and different VCO phase taps to perform frequency

synthesis and phase shifts. In PLLs of Cyclone IV devices, you can reconfigure both

counter settings and phase shift the PLL output clock in real time. You can also change

the charge pump and loop filter components, which dynamically affects PLL

bandwidth. You can use these PLL components to update the output clock frequency,

PLL bandwidth, and phase shift in real time, without reconfiguring the entire FPGA.

The ability to reconfigure the PLL in real time is useful in applications that might

operate at multiple frequencies. It is also useful in prototyping environments,

allowing you to sweep PLL output frequencies and adjust the output clock phase

dynamically. For instance, a system generating test patterns is required to generate

and send patterns at 75 or 150 MHz, depending on the requirements of the device

under test. Reconfiguring PLL components in real time allows you to switch between

two such output frequencies in a few microseconds.

You can also use this feature to adjust clock-to-out (tCO) delays in real time by

changing the PLL output clock phase shift. This approach eliminates the need to

regenerate a configuration file with the new PLL settings.

PLL Reconfiguration Hardware Implementation

The following PLL components are configurable in real time:

■

Pre-scale counter (N)

■

Feedback counter (M)

■

Post-scale output counters (C0–C4)

■

Dynamically adjust the charge pump current (ICP) and loop filter components

(R, C) to facilitate on-the-fly reconfiguration of the PLL bandwidth

EP4CE40 Datasheet(PDF) 96 Page - Altera Corporation