EP4CE40 datasheet(43/488 Pages) ALTERA

43 / 488 page

Chapter 3: Memory Blocks in Cyclone IV Devices

3–7

Memory Modes

November 2011

Altera Corporation

Cyclone IV Device Handbook,

Volume 1

Asynchronous Clear

Cyclone IV devices support asynchronous clears for read address registers, output

registers, and output latches only. Input registers other than read address registers are

not supported. When applied to output registers, the asynchronous clear signal clears

the output registers and the effects are immediately seen. If your RAM does not use

output registers, you can still clear the RAM outputs using the output latch

asynchronous clear feature.

1 Asserting asynchronous clear to the read address register during a read operation

may corrupt the memory content.

Figure 3–5 shows the functional waveform for the asynchronous clear feature.

1 You can selectively enable asynchronous clears per logical memory using the

Quartus II RAM MegaWizard™ Plug-In Manager.

f For more information, refer to the RAM Megafunction User Guide.

There are three ways to reset registers in the M9K blocks:

■

Power up the device

■

Use the aclr signal for output register only

■

Assert the device-wide reset signal using the DEV_CLRn option

Memory Modes

Cyclone IV devices M9K memory blocks allow you to implement fully-synchronous

SRAM memory in multiple modes of operation. Cyclone IV devices M9K memory

blocks do not support asynchronous (unregistered) memory inputs.

M9K memory blocks support the following modes:

■

Single-port

■

Simple dual-port

■

True dual-port

■

Shift-register

■

ROM

■

FIFO

Figure 3–5. Output Latch Asynchronous Clear Waveform

aclr

aclr at latch

clk

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