EP4CE40 datasheet(95/488 Pages) ALTERA

95 / 488 page

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices

5–33

PLL Cascading

October 2012

Altera Corporation

Cyclone IV Device Handbook,

Volume 1

Figure 5–21 shows an example of phase shift insertion using fine resolution through

VCO phase taps method. The eight phases from the VCO are shown and labeled for

reference. In this example, CLK0 is based on 0° phase from the VCO and has the C

value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks

for high time and two VCO clocks for low time. CLK1 is based on the 135° phase tap

from the VCO and has the C value for the counter set to one. The CLK1 signal is also

divided by four. In this case, the two clocks are offset by 3

fine. CLK2 is based on the

0° phase from the VCO but has the C value for the counter set to three. This creates a

delay of two

coarse (two complete VCO periods).

You can use the coarse and fine phase shifts to implement clock delays in

Cyclone IV devices.

Cyclone IV devices support dynamic phase shifting of VCO phase taps only. The

phase shift is configurable for any number of times. Each phase shift takes about one

scanclk

cycle, allowing you to implement large phase shifts quickly.

PLL Cascading

Cyclone IV devices allow cascading between general purpose PLLs and multipurpose

PLLs in normal or direct mode through the GCLK network. If your design cascades

PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the

destination (downstream) PLL must have a high-bandwidth setting.

1 PLL_6 and PLL7 have upstream cascading capability only.

1 PLL cascading is not supported when used in transceiver applications.

Figure 5–21. Delay Insertion Using VCO Phase Output and Counter Delay Time

td0-1

td0-2

1/8 tVCO

tVCO

135

180

225

270

315

CLK0

CLK1

CLK2

EP4CE40 Datasheet(PDF) 95 Page - Altera Corporation

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