TUSB7340 datasheet(104/117 Pages) TI1

104 / 117 page

TUSB7320, TUSB7340

SLLSE76M – MARCH 2011 – REVISED JULY 2015

www.ti.com

9 Power Supply Recommendations

9.1 Power-Up and Power-Down Sequencing

The host controller contains both 1.1-V and 3.3-V power terminals. The following power-up and power-down

sequences describe how power is applied to these terminals.

In addition, the host controller has three resets: PERST#, GRST#, and an internal power- on reset. These resets

are fully described in the next section. The following power-up and power-down sequences describe how

PERST# is applied to the host controller.

The application of the PCI Express reference clock (PCIE_REFCLK) is important to the power-up/-down

sequence and is included in the following power-up and power-down descriptions.

9.1.1 Power-Up Sequence

1. Assert PERST# to the device.

2. Apply 1.1-V and 3.3-V voltages.

3. GRST# must remain asserted until both the 1.1-V and 3.3-V voltages have reached the minimum

recommended operating voltage, see Recommended Operating Conditions. If a 24 MHz or 48 MHz

reference clock is used instead of a crystal, GRST# must remain asserted until the 24 MHz or 48 MHz clock

is stable.

4. Apply a stable PCI Express reference clock.

5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two delay

requirements are satisfied:

Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit satisfies the

requirement for stable device clocks by the de-assertion of PERST.

Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable power by

the de-assertion of PERST.

See the power-up sequencing diagram in Figure 23.

Figure 23. Power-Up Sequence

104

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TUSB7340 Datasheet(PDF) 104 Page - Texas Instruments