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TUSB7340 Datasheet(PDF) 105 Page - Texas Instruments |
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TUSB7340 Datasheet(HTML) 105 Page - Texas Instruments |
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105 / 117 page  VDD11 VDDA_3P3 and VDD33 PCIE_REFCLK PERST# TUSB7320, TUSB7340 www.ti.com SLLSE76M – MARCH 2011 – REVISED JULY 2015 Power-Up and Power-Down Sequencing (continued) 9.1.2 Power-Down Sequence 1. Assert PERST# to the device. 2. Remove the reference clock. 3. Remove the 3.3-V and 1.1-V voltages See the power power-down sequencing diagram in Figure 24. If the VDD33_AUX terminal is to remain powered after a system shutdown, then the host controller power-down sequence is exactly the same as shown in Figure 24. Figure 24. Power-Down Sequence 9.2 PCI Express Power Management The TUSB73X0 includes the MSI-X Table and PBA in memory mapped register space (see Table 199). These registers are accessible through the address programmed into the Base Address Register 2/3. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 105 Product Folder Links: TUSB7320 TUSB7340 |
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