R5F10WMDA datasheet(113/126 Pages) RENESAS

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RL78/L13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA =

−40 to +105°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 113 of 123

3.6.3 Comparator

(TA =

−40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage range

Ivref

VDD

−

1.4

Ivcmp

−0.3

VDD +

0.3

Output delay

VDD = 3.0 V

Input slew rate > 50 mV/

μs

Comparator high-speed mode,

standard mode

1.2

μs

Comparator high-speed mode,

window mode

2.0

μs

Comparator low-speed mode,

standard mode

3.0

5.0

μs

High-electric-potential

reference voltage

VTW+

Comparator high-speed mode,

window mode

0.66VDD 0.76VDD 0.86VDD

Low-electric-potential

reference voltage

VTW

−

Comparator high-speed mode,

window mode

0.14VDD 0.24VDD 0.34VDD

Operation stabilization

wait time

tCMP

100

μs

Internal reference

output voltageNote

VBGR

2.4 V

≤ VDD ≤ 5.5 V, HS (high-speed main) mode

1.38

1.45

1.50

Note

Cannot be used in subsystem clock operation and STOP mode.

3.6.4 POR circuit characteristics

(TA =

−40 to +105°C, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Detection voltage

VPOR

When power supply rises

1.45

1.51

1.57

VPDR

When power supply falls

1.44

1.50

1.56

Minimum pulse widthNote

TPW

300

μs

Note

This is the time required for the POR circuit to execute a reset operation when VDD falls below VPDR. When the

microcontroller enters STOP mode and when the main system clock (fMAIN) has been stopped by setting bit 0

(HIOSTOP) and bit 7 (MSTOP) of the clock operation status control register (CSC), this is the time required for

the POR circuit to execute a reset operation between when VDD falls below 0.7 V and when VDD rises to VPOR or

higher.

Supply voltage (VDD)

TPW

VPOR

VPDR or 0.7 V

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