MSP430F6638IPZ datasheet(35/133 Pages) TI

35 / 133 page

8.25 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I(SVSL)

SVSL current consumption

SVSLE = 0, PMMCOREV = 2

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

200

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

2.0

µA

tpd(SVSL)

SVSL propagation delay

SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1

2.5

µs

SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0

t(SVSL)

SVSL on or off delay time

SVSLE = 0→1, SVSLFP = 1

12.5

µs

SVSLE = 0→1, SVSLFP = 0

100

8.26 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I(SVML)

SVML current consumption

SVMLE = 0, PMMCOREV = 2

SVMLE = 1, PMMCOREV = 2, SVMLFP = 0

200

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1

2.0

µA

tpd(SVML) SVML propagation delay

SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1

2.5

µs

SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0

t(SVML)

SVML on or off delay time

SVMLE = 0→1, SVMLFP = 1

12.5

µs

SVMLE = 0→1, SVMLFP = 0

100

8.27 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

tWAKE-UP-FAST

Wake-up time from LPM2,

LPM3, or LPM4 to active

mode(1)

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 1

fMCLK ≥ 4 MHz

6.5

µs

1 MHz < fMCLK <

4 MHz

8.0

tWAKE-UP-SLOW

Wake-up time from LPM2,

LPM3, or LPM4 to active

mode(2) (3)

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 0

150

165

µs

tWAKE-UP-LPM5

Wake-up time from LPM3.5 or

LPM4.5 to active mode(4)

tWAKE-UP-RESET

Wake-up time from RST or

BOR event to active mode(4)

(1)

This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the

performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in

full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode

Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx

Family User's Guide.

(2)

This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the

performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in

normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode

Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx

Family User's Guide.

(3)

The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by

the performance mode settings as for LPM2, LPM3, and LPM4.

(4)

This value represents the time from the wake-up event to the reset vector execution.

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SLAS566G – JUNE 2010 – REVISED SEPTEMBER 2020

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MSP430F6638IPZ Datasheet(PDF) 35 Page - Texas Instruments

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