MSP430F6638IPZ datasheet(6/133 Pages) TI

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5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from revision F to revision G

Changes from September 18, 2018 to September 10, 2020

Page

• Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1

• Added nFBGA package (ZCA) information throughout document......................................................................1

• Removed package options that are no longer available in Table 6-1, Device Comparison (MSP430F6637,

MSP430F6632, MSP430F6631, and MSP430F6630 in ZQW) ......................................................................... 8

• Updated the list of devices available in the 113-Pin ZQW package in the caption of Figure 7-4 .......................9

• Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.57, Flash Memory ......... 58

• Corrected the connection of the P7SEL.x signal in Figure 9-11, Port P7 (P7.4 to P7.7) Diagram ................ 103

Changes from revision E to revision F

Changes from December 9, 2015 to September 17, 2018

Page

• Added Section 6.1, Related Products ................................................................................................................8

• Added typical conditions statements at the beginning of Section 8, Specifications .........................................20

• Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 8.21, PMM,

Brownout Reset (BOR) .................................................................................................................................... 33

• Updated notes (1) and (2) and added note (3) in Section 8.27, Wake-up Times From Low-Power Modes and

Reset ............................................................................................................................................................... 35

• Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in

Section 8.38, 12-Bit ADC, Timing Parameters, because ADC12CLK is after division..................................... 45

• Removed the note that started "This impedance depends on..." from the "Reference input resistance"

parameter in Section 8.48, 12-Bit DAC, Reference Input Specifications .........................................................53

• Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in Section

8.51, Comparator_B ........................................................................................................................................ 55

• Renamed FCTL4.MGR0 and MGR1 in the fMCLK,MGR parameter in Section 8.57, Flash Memory to be

consistent with header files ..............................................................................................................................58

• Replaced former section Development Tools Support with Section 10.3, Tools and Software ......................115

Changes from revision D to revision E

Changes from August 6, 2013 to December 8, 2015

Page

• Document format and organization changes throughout, including addition of section numbering....................1

• Moved all functional block diagrams to Section 4, Functional Block Diagrams ................................................. 3

• Added USB column to Table 6-1, Family Members ........................................................................................... 8

• Added Section 6, Device Comparison, and moved Table 6-1 to it......................................................................8

• Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in Section 7.2, Signal

Descriptions ..................................................................................................................................................... 13

• Added Section 8.2, ESD Ratings .....................................................................................................................20

• Added note to CVCORE ..................................................................................................................................... 20

• Added note to RPull .......................................................................................................................................... 25

• Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF.......................29

• In VBAT3 parameter description, changed from "VBAT3 ≠ VBAT/3" to "VBAT3 = VBAT/3"....................................... 37

• Changed from fDAC12_0OUT to fDAC12_1OUT in the first row of the Test Conditions for the "Channel-to-channel

crosstalk" parameter.........................................................................................................................................54

• Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from fToggle to 1/fToggle in

Figure 8-22, Crosstalk Test Conditions ............................................................................................................54

MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635, MSP430F6634

MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630

SLAS566G – JUNE 2010 – REVISED SEPTEMBER 2020

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