MSP430F6638IPZ datasheet(45/133 Pages) TI

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8.37 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

AVCC

Analog supply voltage

AVCC and DVCC are connected together,

AVSS and DVSS are connected together,

V(AVSS) = V(DVSS) = 0 V

2.2

3.6

V(Ax)

Analog input voltage range(3) All ADC12 analog input pins Ax

AVCC

IADC12_A

Operating supply current into

AVCC terminal(4)

fADC12CLK = 5 MHz(1)

2.2 V

150

200

µA

3 V

150

250

Input capacitance

Only one terminal Ax can be selected at one

time

2.2 V

Input MUX ON resistance

0 V ≤ VIN ≤ V(AVCC)

200

1900

Ω

(1)

ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0

(2)

The leakage current is specified by the digital I/O input leakage.

(3)

The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the

reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are

required. See Section 8.43 and Section 8.44.

(4)

The internal reference supply current is not included in current consumption parameter IADC12.

8.38 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

fADC12CLK

ADC conversion clock

For specified performance of ADC12 linearity

parameters using an external reference

voltage or AVCC as reference(1)

2.2 V, 3 V

0.45

4.8

5.0

MHz

For specified performance of ADC12 linearity

parameters using the internal reference(2)

0.45

2.4

4.0

For specified performance of ADC12 linearity

parameters using the internal reference(3)

0.45

2.4

2.7

fADC12OSC

Internal ADC12

oscillator(5)

ADC12DIV = 0, fADC12CLK = fADC12OSC

2.2 V, 3 V

4.2

4.8

5.4

MHz

tCONVERT

Conversion time

REFON = 0, Internal oscillator,

ADC12OSC used for ADC conversion clock

2.2 V, 3 V

2.4

3.1

µs

External fADC12CLK from ACLK, MCLK or

SMCLK, ADC12SSEL ≠ 0

13 ×

1 / fADC12CLK

tSample

Sampling time

RS = 400 Ω, RI = 200 Ω, CI = 20 pF,

τ = (RS + RI) × CI (4)

2.2 V, 3 V

1000

(1)

REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,

SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the

specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5 MHz.

(2)

SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1

(3)

SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when

using the ADC12OSC divided by 2.

(4)

Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:

tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance

(5)

The ADC12OSC is sourced directly from MODOSC inside the UCS.

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MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635, MSP430F6634

MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630

SLAS566G – JUNE 2010 – REVISED SEPTEMBER 2020

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