MSP430F6638IPZ datasheet(19/133 Pages) TI

19 / 133 page

Table 7-1. Signal Descriptions (continued)

TERMINAL

I/O(1)

DESCRIPTION

NAME

NO.(4)

ZCA,

ZQW

DVSS3

Digital ground supply

TEST/SBWTCK

Test mode pin; selects digital I/O on JTAG pins

Spy-Bi-Wire input clock

PJ.0/TDO

I/O

General-purpose digital I/O

Test data output port

PJ.1/TDI/TCLK

I/O

General-purpose digital I/O

Test data input or test clock input

PJ.2/TMS

I/O

General-purpose digital I/O

Test mode select

PJ.3/TCK

I/O

General-purpose digital I/O

Test clock

RST/NMI/SBWTDIO

I/O

Reset input (active low)(3)

Nonmaskable interrupt input

Spy-Bi-Wire data input/output

P6.0/CB0/A0

I/O

General-purpose digital I/O

Comparator_B input CB0

Analog input A0 – ADC (not available on F6632, F6631, and F6630 devices)

P6.1/CB1/A1

I/O

General-purpose digital I/O

Comparator_B input CB1

Analog input A1 – ADC (not available on F6632, F6631, and F6630 devices)

P6.2/CB2/A2

I/O

General-purpose digital I/O

Comparator_B input CB2

Analog input A2 – ADC (not available on F6632, F6631, and F6630 devices)

P6.3/CB3/A3

100

I/O

General-purpose digital I/O

Comparator_B input CB3

Analog input A3 – ADC (not available on F6632, F6631, and F6630 devices)

Reserved

N/A

E5,

E6,

E8,

F4,

F5,

F8,

G5,

G8,

H5,

H8,

Reserved. TI recommends connecting to ground (DVSS, AVSS).

(1)

I = input, O = output, N/A = not available on this package offering

(2)

VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, CVCORE.

(3)

When this pin is configured as reset, the internal pullup resistor is enabled by default.

(4)

See the Package Option Addendum in Section 11 to determine which devices are available in each package.

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MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635, MSP430F6634

MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630

SLAS566G – JUNE 2010 – REVISED SEPTEMBER 2020

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