MSP430F6638IPZ datasheet(40/133 Pages) TI

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8.33 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

(see Figure 8-13 and Figure 8-14)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

tSTE,LEAD

STE lead time, STE low to clock

PMMCOREV = 0

1.8 V

3 V

PMMCOREV = 3

2.4 V

3 V

tSTE,LAG

STE lag time, Last clock to STE high

PMMCOREV = 0

1.8 V

3 V

PMMCOREV = 3

2.4 V

3 V

tSTE,ACC

STE access time, STE low to SOMI data out

PMMCOREV = 0

1.8 V

3 V

PMMCOREV = 3

2.4 V

3 V

tSTE,DIS

STE disable time, STE high to SOMI high impedance

PMMCOREV = 0

1.8 V

3 V

PMMCOREV = 3

2.4 V

3 V

tSU,SI

SIMO input data setup time

PMMCOREV = 0

1.8 V

3 V

PMMCOREV = 3

2.4 V

3 V

tHD,SI

SIMO input data hold time

PMMCOREV = 0

1.8 V

3 V

PMMCOREV = 3

2.4 V

3 V

tVALID,SO

SOMI output data valid time(2)

UCLK edge to SOMI valid,

CL = 20 pF,

PMMCOREV = 0

1.8 V

3 V

UCLK edge to SOMI valid,

CL = 20 pF,

PMMCOREV = 3

2.4 V

3 V

tHD,SO

SOMI output data hold time(3)

CL = 20 pF,

PMMCOREV = 0

1.8 V

3 V

CL = 20 pF,

PMMCOREV = 3

2.4 V

3 V

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))

For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.

(2)

Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 8-13 and Figure 8-14.

(3)

Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure

8-13 and Figure 8-14.

MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635, MSP430F6634

MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630

SLAS566G – JUNE 2010 – REVISED SEPTEMBER 2020

www.ti.com

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