MSP430F6638IPZ datasheet(67/133 Pages) TI

67 / 133 page

Table 9-9. Port Mapping Mnemonics and Functions (continued)

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PM_TB0CCR6B

Timer TB0 CCR6 capture input CCI6B

Timer TB0: TB0.6 compare output Out6

PM_UCA0RXD

USCI_A0 UART RXD (Direction controlled by USCI – input)

PM_UCA0SOMI

USCI_A0 SPI slave out master in (direction controlled by USCI)

PM_UCA0TXD

USCI_A0 UART TXD (Direction controlled by USCI – output)

PM_UCA0SIMO

USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0CLK

USCI_A0 clock input/output (direction controlled by USCI)

PM_UCB0STE

USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)

PM_UCB0SOMI

USCI_B0 SPI slave out master in (direction controlled by USCI)

PM_UCB0SCL

USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0SIMO

USCI_B0 SPI slave in master out (direction controlled by USCI)

PM_UCB0SDA

USCI_B0 I2C data (open drain and direction controlled by USCI)

PM_UCB0CLK

USCI_B0 clock input/output (direction controlled by USCI)

PM_UCA0STE

USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

PM_MCLK

–

MCLK

Reserved

Reserved for test purposes. Do not use this setting.

Reserved

Reserved for test purposes. Do not use this setting.

20–30

Reserved

None

DVSS

31 (0FFh)(1)

PM_ANALOG

Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents

when applying analog signals.

(1)

The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored,

which results in a maximum value of 31.

Table 9-10 lists the default values for all pins that support port mapping.

Table 9-10. Default Mapping

PxMAPy

MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

P2.0/P2MAP0

PM_UCB0STE,

PM_UCA0CLK

USCI_B0 SPI slave transmit enable (direction controlled by USCI – input),

USCI_A0 clock input/output (direction controlled by USCI)

P2.1/P2MAP1

PM_UCB0SIMO,

PM_UCB0SDA

USCI_B0 SPI slave in master out (direction controlled by USCI),

USCI_B0 I2C data (open drain and direction controlled by USCI)

P2.2/P2MAP2

PM_UCB0SOMI,

PM_UCB0SCL

USCI_B0 SPI slave out master in (direction controlled by USCI),

USCI_B0 I2C clock (open drain and direction controlled by USCI)

P2.3/P2MAP3

PM_UCB0CLK,

PM_UCA0STE

USCI_B0 clock input/output (direction controlled by USCI),

USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

P2.4/P2MAP4

PM_UCA0TXD,

PM_UCA0SIMO

USCI_A0 UART TXD (direction controlled by USCI – output),

USCI_A0 SPI slave in master out (direction controlled by USCI)

P2.5/P2MAP5

PM_UCA0RXD,

PM_UCA0SOMI

USCI_A0 UART RXD (direction controlled by USCI – input),

USCI_A0 SPI slave out master in (direction controlled by USCI)

P2.6/P2MAP6/R03

PM_NONE

–

DVSS

P2.7/P2MAP7/LCDREF/R13

PM_NONE

–

DVSS

9.12.3 Oscillator and System Clock

The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz

watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-

frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally

controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS module is designed to meet

the requirements of both low system cost and low power consumption. The UCS module features digital

frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency

www.ti.com

MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635, MSP430F6634

MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630

SLAS566G – JUNE 2010 – REVISED SEPTEMBER 2020

Submit Document Feedback

Product Folder Links: MSP430F6638 MSP430F6637 MSP430F6636 MSP430F6635 MSP430F6634

MSP430F6633 MSP430F6632 MSP430F6631 MSP430F6630

MSP430F6638IPZ Datasheet(PDF) 67 Page - Texas Instruments

MSP430F6638IPZ Datasheet(HTML) 67 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL