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HC705E5GRS/D Datasheet(PDF) 105 Page - NXP Semiconductors |
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HC705E5GRS/D Datasheet(HTML) 105 Page - NXP Semiconductors |
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105 / 148 page  Synchronous Serial Interface (SSI) SSI During Wait Mode MC68HC705E5 — Rev. 1.0 General Release Specification Synchronous Serial Interface (SSI) 12.6 SSI During Wait Mode The CPU clock halts during wait mode, but the SSI remains active. If interrupts are enabled, an SSI interrupt will cause the processor to exit wait mode. 12.7 SSI Pin Configuration When the SSI is enabled via the SE bit of the SCR ($0A), the port B data direction register bits 3–5 relinquish control to the SSI as directed by the combination of the SE, MSTR, and SDIR bits. The states of the port B DDR bits are not altered by the SSI. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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