STM32U375CE datasheet(139/222 Pages) STMICROELECTRONICS

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Table 86. I/O static characteristics

The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance, TT_a refers to

any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology

or TTL parameters. The coverage of these requirements is shown in the figure below.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(1)

I/O input low

‑level voltage

1.08 V ≤ VDDIOx ≤ 3.6 V

0.3 VDDIOx

All I/Os

0.38

VDDIOx(2)

VIH(1)

I/O input high-level voltage

1.08 V ≤ VDDIOx ≤ 3.6 V

0.7 VDDIOx

All I/Os

0.5 VDDIOx

+ 0.2(2)

Vhys(2) Input hysteresis

TT_xx, FT_xx I/Os

250

Ilkg(2)(3) Input leakage current

All I/Os except

FT_u, FT_d, FT_o,

FT_t,

TT_xx

VIN ≤ Max (VDDxxx)(4)

150

Max (VDDXXX) < VIN(5) ≤ Max

(VDDXXX) + 1 V

2000

Max (VDDXXX) + 1 V < VIN ≤ 5.5 V(5)

500

FT_o I/Os

VIN ≤ Max (VDDXXX)

Max (VDDXXX) ≤ VIN ≤ Max (VDDXXX)

+ 1 V

500

Max (VDDXXX) +1 V ≤ VIN ≤ 5.5 V(5)

200

FT_u I/O

VIN≤ Max (VDDXXX)

200

Max (VDDXXX) ≤ VIN ≤ Max (VDDXXX)

+ 1 V

2500

Max (VDDXXX) ≤ VIN ≤ 5.5

500

FT_t

VIN ≤ Max (VDDXXX)

300

Max (VDDXXX) < VIN ≤ Max (VDDXXX)

+ 1 V(5)

3000

Max (VDDXXX) + 1 V < VIN ≤ 5.5 V(5)

600

Ilkg

(2)(3)

Input leakage current

TT_xx I/Os

VIN ≤ Max (VDDXXX)

500

RPU

Weak pull

‑up equivalent

resistor(6)

kΩ

RPD

Weak pulldown equivalent

resistor(6)

CIO

I/O pin capacitance

1. Refer to Figure 36. I/O input characteristics (all I/Os except BOOT0).

2. Specified by design. Not tested in production.

3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula:

ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] × Ilkg max.

4. Max (VDDxxx) is the maximum value of all the I/O supplies. The I/O supplies depend on the I/O structure options, as described in Table 20.

5. To sustain a voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull

‑up and pull‑down resistors must be disabled.

6. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS

contribution to the series resistance is minimal (~10% order).

STM32U375xx

Electrical characteristics

DS14861 - Rev 2

page 139/222

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