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STM32U375CE Datasheet(PDF) 176 Page - STMicroelectronics |
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STM32U375CE Datasheet(HTML) 176 Page - STMicroelectronics |
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176 / 222 page ![]() Figure 62. SPI timing diagram - master mode th(MI) tc(SCK) tw(SCKH) tw(SCKL) tsu(MI) NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 MOSI output MISO input First bit OUT Last bit OUT Next bits OUT First bit IN Last bit IN Next bits IN CPHA=1 CPOL=0 CPHA=1 CPOL=1 High tv(MO) th(MO) Note: Measurement points are done at 0.3 VDD and 0.7 VDD levels. 5.3.35 SAI characteristics Unless otherwise specified, the parameters given in Table 122 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 27, with the following configuration: • Output speed set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • Measurement points done at 0.5 × VDD level • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • Voltage scaling range 1 Refer to Table 86. I/O static characteristics for more details on the input/output alternate function characteristics (SCK, SD, FS). Table 122. SAI characteristics Evaluated by characterization. Not tested in production. Symbol Parameter Conditions Min Max Unit fMCK SAI main clock output - - 50 MHz fSCK SAI clock frequency(1) Master transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - 28.5 Master transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - 28.5/19.5(2)(3) Master receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - 31/21.5(3) Slave transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - 30 Slave transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - 30/20.5(2) Slave receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - 50 STM32U375xx Electrical characteristics DS14861 - Rev 2 page 176/222 |
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