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STM32U375CE Datasheet(PDF) 173 Page - STMicroelectronics |
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STM32U375CE Datasheet(HTML) 173 Page - STMicroelectronics |
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173 / 222 page ![]() Figure 58. USART timing diagram in SPI master mode 1/fCK tw(CKH) tw(CKL) CPHA=0 CPOL=0 CPHA=0 CPOL=1 TX output RX input MSB OUT LSB OUT BIT1 OUT MSB IN LSB IN BIT6 IN CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(RX) tv(TX) th(TX) th(RX) Figure 59. USART timing diagram in SPI slave mode NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 TX output RX input th(RX) tw(CKL) tw(CKH) 1/fCK th(NSS) tsu(NSS) tv(TX) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(TX) Last bit IN tsu(RX) 5.3.34 SPI characteristics Unless otherwise specified, the parameters given in Table 121 are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 27. • Output speed set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • Measurement points done at 0.5 × VDD level • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V Refer to Table 86. I/O static characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). STM32U375xx Electrical characteristics DS14861 - Rev 2 page 173/222 |
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