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STM32U375CE Datasheet(PDF) 171 Page - STMicroelectronics

Part # STM32U375CE
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 144 DMIPS, 1 MB flash memory, 256 KB SRAM, SMPS
PDF  222 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U375CE Datasheet(HTML) 171 Page - STMicroelectronics

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•
I3C SDR-only as controller
•
I3C SDR-only as target
•
I3C SCL bus clock frequency up to 12.5 MHz
The parameters given in Table 118 below are obtained with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
I/O Compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
The I3C timings are in line with the MIPI specification, except for the ones given in Table 118, I3C open-drain
measured timing. For tSU_OD, this can be mitigated by increasing the corresponding SCL low duration in the
I3C_TIMINGR0 register. For further details refer to AN5879.
Table 118. Open drain timing measurements
Evaluated by characterization. Not tested in production.
Symbol
Parameter
Conditions
Min
Unit
tSU_OD
SDA data setup time during open drain mode
Controller
1.71 V ≤ VDDIOX ≤ 3.6 V
21(1)
ns
Controller
1.08 V ≤ VDDIO2 ≤ 1.32 V
24.5(1)
1. SDA data setup time during open drain mode is required to be Min 3ns in the MIPI specification.
Table 119. Push pull timing measurements
Evaluated by characterization. Not tested in production.
Symbol
Parameter
Conditions
Max
Unit
tSCO
Clock in to data out for
target
Target
1.71 V ≤ VDDIOX ≤ 3.6
V
11.5
ns
Target
1.2 V ≤ VDDIO2 ≤ 1.32 V
12
Target
1.08 V ≤ VDDIO2 ≤ 1.2 V
14(1)
1. tSCO clock in to data out is required to be Max 12 ns in MIPI specification.
5.3.33
USART characteristics
Unless otherwise specified, the parameters given in Table 120 are derived from tests performed under the
ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in not found, with the
following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, CK, TX, RX for USART).
STM32U375xx
Electrical characteristics
DS14861 - Rev 2
page 171/222



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