STM32U375CE datasheet(168/222 Pages) STMICROELECTRONICS

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Figure 54. OCTOSPI HyperBus write

NCS

Access latency

Latency count

Command address

47:40 39:32 31:24 23:16

15:8

7:0

Dn+1

Host drives DQ[7:0] and the memory drives RWDS.

Host drives DQ[7:0] and RWDS.

CLK, NCLK

RWDS

DQ[7:0]

tw(CS)

tv(RWDS)

tv(CLK)

th(CLK)

High = 2x latency count

Low = 1x latency count

Read write recovery

th(OUT)

tv(OUT)

th(OUT)

tv(OUT)

th(OUT)

tv(OUT)

5.3.29

SD/SDIO/e.MMC card host interfaces (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 114 and Table 115 are derived from tests performed

under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 27, with

the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF, unless otherwise specified

•

Measurement points done at 0.5 × VDD level

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling range 1

Refer to Table 86. I/O static characteristics for more details on the input/output alternate function characteristics.

Table 114. SD/e.MMC characteristics (VDD = 2.7 V to 3.6 V)

Evaluated by characterization. Not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPP

Clock frequency in data transfer mode

96(1)

MHz

tW(CKL)

Clock low time

fPP = 48 MHz

9.5

10.5

tW(CKH)

Clock high time

fPP = 48 MHz

9.5

10.5

CMD, D inputs (referenced to CK) in e.MMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) modes

tISU

Input setup time HS

tIH

Input hold time HS

1.5

tIDW(3)

Input valid window (variable window)

4.5

CMD, D outputs (referenced to CK) in e.MMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) modes

tOV

Output valid time HS

6.6

tOH

Output hold time HS

CMD, D inputs (referenced to CK) in SD default mode

tISU

Input setup time SD

tIH

Input hold time SD

0.5

STM32U375xx

Electrical characteristics

DS14861 - Rev 2

page 168/222

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