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R5F72115D160FPV Datasheet(PDF) 34 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 34 Page - Renesas Technology Corp

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Section 1 Overview
Rev. 2.00 May. 08, 2008 Page 10 of 1200
REJ09B0344-0200
Classification
Symbol
I/O
Name
Function
MD1, MD0
I
Mode set
Sets the operating mode. Do not
change the signal levels on these
pins during operation.
MD_CLK2,
MD_CLK0
I
Clock mode set
Sets the clock operating mode. Do
not change the signal levels on these
pins during operation.
FWE
I
Flash memory
write enable
Pin for flash memory. Flash memory
can be protected against writing or
erasure through this pin.
ASEMD
I
Debugging mode Enables the E10A-USB emulator
functions.
Input a high level to operate the LSI
in normal mode (not in debugging
mode). To operate it in debugging
mode, apply a low level to this pin on
the user system board.
Operating mode
control
TESTMD
I
Test mode
Always fix this input pin low.
Do not input a high level to this pin.
This may cause malfunction or
permanent failure of this LSI.
RES
I
Power-on reset
This LSI enters the power-on reset
state when this signal goes low.
MRES
I
Manual reset
This LSI enters the manual reset
state when this signal goes low.
WDTOVF
O
Watchdog timer
overflow
Outputs an overflow signal from the
WDT.
System control
BREQ
I
Bus-mastership
request
A low level is input to this pin when
an external device requests the
release of the bus mastership.
BACK
O
Bus-mastership
request
acknowledge
Indicates that the bus mastership
has been released to an external
device. Reception of the
BACK
signal informs the device which has
output the
BREQ signal that it has
acquired the bus.



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