R5F72115D160FPV datasheet(30/1228 Pages) RENESAS

30 / 1228 page

Section 1 Overview

Rev. 2.00 May. 08, 2008 Page 6 of 1200

REJ09B0344-0200

Items

Specification

2C bus interface 3

(IIC3)

• One channel

• Master mode and slave mode supported

I/O ports

• Input or output can be selected for each bit

A/D converter (ADC)

• 12-bit resolution

• Eight input channels

• Sampling can be carried out simultaneously on three channels.

• A/D conversion request by the external trigger or timer trigger

D/A converter (DAC)

• 8-bit resolution

• Two output channels

User break controller

(UBC)

• Four break channels

• Addresses, type of access, and data size can all be set as break

conditions

User debugging

interface (H-UDI)

• E10A emulator support

• JTAG-standard pin assignment

• Realtime branch trace

Advanced user

debugger II (AUD- II)

• Six output pins

• Branch source address/destination address trace

• Window data trace

• Full trace

All trace data can be output by interrupting CPU operation

• Realtime trace

Trace data can be output within the range where CPU operation is not

interrupted

WAVE interface

(WAVEIF)

• Myway Labs realtime CPU scope “WAVETM” (WAVE1.0 Level C)

supported

On-chip ROM

• 512 Kbytes

On-chip RAM

• Four pages

• 32 Kbytes

Power supply voltage

• Vcc: 1.4 to 1.6 V

• VccQ: 3.0 to 3.6 V

• AVcc: 4.5 to 5.5 V

Packages

• LQFP2020-144 (0.5 pitch): R5F72115D160FPV

R5F72115D160FPV Datasheet(PDF) 30 Page - Renesas Technology Corp

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