R5F72115D160FPV datasheet(97/1228 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 May. 08, 2008 Page 73 of 1200

REJ09B0344-0200

4.5

Changing the Frequency

The frequency of the internal clock (I

φ) and peripheral clock (Pφ) can be changed either by

changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All

of these are controlled by software through the frequency control register (FRQCR). The methods

are described below.

4.5.1

Changing the Multiplication Rate

A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. When the

multiplication rate is changed, the LSI temporarily stops automatically and the internal watchdog

timer (WDT) starts counting the settling time. When the count of the WDT overflows, the LSI

restarts operating with the set clock frequency. The following shows this setting procedure.

1. In the initial state, the multiplication rate of PLL circuit 1 is 1 time.

2. Set a value that will become the specified oscillation settling time in the WDT and stop the

WDT. The following must be set:

WTCSR.TME

= 0: WDT stops

WTCSR.CKS[2:0]: Division ratio of WDT count clock

WTCNT counter: Initial counter value

For setting of the counter, determine the overflow period with the frequency after the

peripheral clock (P

φ) setting change.

3. Set the desired value in the STC[1:0] bits. The division ratio can also be set in the IFC[2:0] and

PFC[2:0] bits.

4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral

clocks both stop and the WDT is supplied with the clock. The clock will continue to be output

at the CK pin. This state is the same as software standby mode. Whether or not registers are

initialized depends on the module. For details, see table 23.4 in section 23, Power-Down

Modes.

5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins

operating again. The WDT stops counting after it overflows.

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