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R5F72115D160FPV Datasheet(PDF) 98 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 98 Page - Renesas Technology Corp |
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98 / 1228 page  Section 4 Clock Pulse Generator (CPG) Rev. 2.00 May. 08, 2008 Page 74 of 1200 REJ09B0344-0200 4.5.2 Changing the Division Ratio Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is not. 1. In the initial state, IFC[2:0] = B'000 and PFC[2:0] = B'011. 2. Set the desired value in the IFC[2:0] and PFC[2:0] bits. The values that can be set are limited by the clock operating mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, this LSI will malfunction. 3. After the register bits (IFC[2:0] and PFC[2:0]) have been set, the clock is supplied of the new division ratio. Note: When executing the SLEEP instruction after the frequency has been changed, be sure to read the frequency control register (FRQCR) three times before executing the SLEEP instruction. |
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