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R5F72115D160FPV Datasheet(PDF) 67 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 67 Page - Renesas Technology Corp |
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67 / 1228 page  Section 2 CPU Rev. 2.00 May. 08, 2008 Page 43 of 1200 REJ09B0344-0200 Compatibility Instruction Instruction Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A MOVRT Rn 0000nnnn00111001 ~T → Rn 1 ⎯ Yes MOVT Rn 0000nnnn00101001 T → Rn 1 ⎯ Yes Yes Yes MOVU.B @(disp12,Rm),Rn 0011nnnnmmmm0001 1000dddddddddddd (disp + Rm) → zero extension → Rn 1 ⎯ Yes MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 1001dddddddddddd (disp × 2 + Rm) → zero extension → Rn 1 ⎯ Yes NOTT 0000000001101000 ~T → T 1 Ope- ration result Yes PREF @Rn 0000nnnn10000011 (Rn) → operand cache 1 ⎯ Yes Yes SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm → swap lower 2 bytes → Rn 1 ⎯ Yes Yes Yes SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm → swap upper and lower words → Rn 1 ⎯ Yes Yes Yes XTRCT Rm,Rn 0010nnnnmmmm1101 Middle 32 bits of Rm:Rn → Rn 1 ⎯ Yes Yes Yes |
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