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R5F72115D160FPV Datasheet(PDF) 90 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 90 Page - Renesas Technology Corp |
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90 / 1228 page ![]() Section 4 Clock Pulse Generator (CPG) Rev. 2.00 May. 08, 2008 Page 66 of 1200 REJ09B0344-0200 4.3 Clock Operating Modes Table 4.2 shows the relationship between the combinations of the mode control pins (MD_CLK2 and MD_CLK0) and the clock operating modes. Table 4.3 shows the usable frequency ranges in the clock operating modes. Table 4.2 Clock Operating Modes Pin Values Clock I/O Mode MD_CLK2 MD_CLK0 Source Output PLL Circuit 2 On/Off PLL Circuit 1 On/Off CK Frequency 6 1 0 EXTAL or crystal resonator CK On ( × 4) On ( × 1, 2, 4) (EXTAL or crystal resonator) × 4 • Mode 6 The frequency of the signal received from the EXTAL pin or crystal oscillator is quadrupled by the PLL circuit 2 before it is supplied to the LSI as the clock signal. This allows a crystal with a lower frequency to be used. Either a crystal resonator with a frequency in the range from 8 to 10 MHz or an external signal in the same frequency range input on the EXTAL pin can be used. When the CK output is in use, the frequency range is from 32 to 40 MHz. When an input signal on the EXTAL pin is in use, the XTAL pin should be left open. |
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