R5F72115D160FPV datasheet(60/1228 Pages) RENESAS

60 / 1228 page

Section 2 CPU

Rev. 2.00 May. 08, 2008 Page 36 of 1200

REJ09B0344-0200

Classification Types

Operation

Code

Function

No. of

Instructions

ADD

Binary addition

ADDC

Binary addition with carry

ADDV

Binary addition with overflow check

CMP/cond Comparison

CLIPS

Signed saturation value comparison

CLIPU

Unsigned saturation value comparison

DIVS

Signed division (32

÷ 32)

DIVU

Unsigned division (32

÷ 32)

DIV1

One-step division

Arithmetic

operations

DIV0S

Initialization of signed one-step division

DIV0U

Initialization of unsigned one-step division

DMULS

Signed double-precision multiplication

DMULU

Unsigned double-precision multiplication

Decrement and test

EXTS

Sign extension

EXTU

Zero extension

MAC

Multiply-and-accumulate, double-precision

multiply-and-accumulate operation

MUL

Double-precision multiply operation

MULR

Signed multiplication with result storage in Rn

MULS

Signed multiplication

MULU

Unsigned multiplication

NEG

Negation

NEGC

Negation with borrow

SUB

Binary subtraction

SUBC

Binary subtraction with borrow

SUBV

Binary subtraction with underflow

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