R5F72115D160FPV datasheet(99/1228 Pages) RENESAS

99 / 1228 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 May. 08, 2008 Page 75 of 1200

REJ09B0344-0200

4.6

Notes on Board Design

4.6.1

Note on Using an External Crystal Resonator

Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as

possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency,

the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring

wiring patterns close to these components.

CL1

CL2

EXTAL

XTAL

Signal lines prohibited

This LSI

The values for CL1 and CL2

should be determined after

consultation with the crystal

resonator manufacturer.

Note:

Reference value

CL1 = 20 pF

CL2 = 20 pF

Figure 4.2 Note on Using a Crystal Resonator

4.6.2

Note on Bypass Capacitor

A multilayer ceramic capacitor should be inserted for each pair of Vss and Vcc as a bypass

capacitor as many as possible. The bypass capacitor must be inserted as close to the power supply

pins of the LSI as possible. Note that the capacitance and frequency characteristics of the bypass

capacitor must be appropriate for the operating frequency of the LSI.

4.6.3

Note on Using a PLL Oscillation Circuit

In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power

supply pins must be as short as possible and pattern width must be as wide as possible to reduce

inductive interference.

Since the analog power supply pins of the PLL are sensitive to the noise, the system may

malfunction due to inductive interference at the other power supply pins. To prevent such

malfunction, the analog power supply pin Vcc and digital power supply pin VccQ should not

supply the same resources on the board if at all possible.

R5F72115D160FPV Datasheet(PDF) 99 Page - Renesas Technology Corp