R5F72115D160FPV datasheet(102/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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102 / 1228 page

Section 5 Exception Handling

Rev. 2.00 May. 08, 2008 Page 78 of 1200

REJ09B0344-0200

Type

Exception Handling

Priority

Multi-function timer pulse unit 2S (MTU2S)

Port output enable 2 (POE2): OEI3

interrupt

2C bus interface 3 (IIC3)

Interrupt

On-chip peripheral modules

Serial communication interface with FIFO

(SCIF)

Trap instruction (TRAPA instruction)

General illegal instructions (undefined code)

Instruction

Slot illegal instructions (undefined code placed directly after a delayed

branch instruction*

1, instructions that rewrite the PC*2, 32-bit

instructions*

3, RESBANK instruction, DIVS instruction, and DIVU

instruction)

High

Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF.

2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.

3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,

BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,

MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.

R5F72115D160FPV Datasheet(PDF) 102 Page - Renesas Technology Corp