R5F72115D160FPV datasheet(55/1228 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 May. 08, 2008 Page 31 of 1200

REJ09B0344-0200

2.3.3

Instruction Format

The instruction formats and the meaning of source and destination operands are described below.

The meaning of the operand depends on the instruction code. The symbols used are as follows:

• xxxx: Instruction code

• mmmm: Source register

• nnnn: Destination register

• iiii: Immediate data

• dddd: Displacement

Table 2.9

Instruction Formats

Source

Operand

Destination

Operand

Example

0 format

xxxx

—

NOP

—

nnnn: Register

direct

MOVT

Control register or

system register

nnnn: Register

direct

STS

MACH,Rn

R0 (Register direct) nnnn: Register

direct

DIVU

R0,Rn

Control register or

system register

nnnn: Register

indirect with pre-

decrement

STC.L

SR,@-Rn

mmmm: Register

direct

R15 (Register

indirect with pre-

decrement)

MOVMU.L Rm,@-R15

n format

xxxx

nnnn

R15 (Register

indirect with post-

increment)

nnnn: Register

direct

MOVMU.L @R15+,Rn

R0 (Register direct) nnnn: (Register

indirect with post-

increment)

MOV.L

R0,@Rn+

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