R5F72115D160FPV datasheet(27/1228 Pages) RENESAS

27 / 1228 page

Section 1 Overview

Rev. 2.00 May. 08, 2008 Page 3 of 1200

REJ09B0344-0200

Items

Specification

ROM cache

• Instruction/data separation system

• Instruction prefetch cache: Full/set associative

• Instruction prefetch miss cache: Full/set associative

• Data cache: Full/set associative

• Line size: 16 bytes

• Hardware prefetch function (continuous/branch prefetch)

Interrupt controller

(INTC)

• Nine external interrupt pins (NMI and IRQ7 to IRQ0)

• On-chip peripheral interrupts: Priority level set for each module

• 16 priority levels available

• Register bank enabling fast register saving and restoring in interrupt

processing

Bus state controller

(BSC)

• Address space divided into eight areas (0 to 7), each a maximum of 64

Mbytes

• External bus: 8 or 16 bits

• The following features settable for each area independently

⎯ Supports both big endian and little endian for data access

⎯ Bus size (8 or 16 bits): Available sizes depend on the area.

⎯ Number of access wait cycles (different wait cycles can be

specified for read and write access cycles in some areas)

⎯ Idle wait cycle insertion (between same area access cycles or

different area access cycles)

⎯ Specifying the memory to be connected to each area enables

direct connection to SRAM, SRAM with byte selection, SDRAM,

and burst ROM (clocked synchronous or asynchronous). The

address/data multiplexed I/O (MPX) interface is also available.

⎯ Outputs a chip select signal (

CS0 to CS7) according to the target

area (

CS assert or negate timing can be selected by software)

• SDRAM refresh

Auto refresh or self refresh mode selectable

• SDRAM burst access

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