R5F72115D160FPV datasheet(96/1228 Pages) RENESAS

96 / 1228 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 May. 08, 2008 Page 72 of 1200

REJ09B0344-0200

4.4.3

AD Clock Frequency Control Register (ACLKCR)

ACLKCR is an 8-bit readable/writable register that can be accessed only in byte units. ACLKCR

is only initialized to H'43 by a power-on reset, but retains its previous value by a manual reset or

in software standby mode.

7654321

01000011

R/W

Bit:

Initial value:

R/W:

ASSCS[1:0]

ASDIVS[1:0]

----

Bit

Bit Name

Initial

Value

R/W

Description

7, 6

ASSCS[1:0]

R/W

Source Clock Select

These bits select the source clock.

00: Clock stoppage

01: PLL1 output clock

10: Reserved (setting prohibited)

11: Reserved (setting prohibited)

5 to 2

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

1, 0

ASDIVS[1:0] 11

R/W

Division Ratio Select

These bits specify the frequency division ratio of the

source clock. Set these bits so that the output clock is

40 MHz or less, and also an integer multiple of the

peripheral clock frequency (P

φ).

00:

× 1 time

01:

× 1/2 time

10: Setting prohibited

11:

× 1/4 time

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