R5F72115D160FPV datasheet(36/1228 Pages) RENESAS

36 / 1228 page

Section 1 Overview

Rev. 2.00 May. 08, 2008 Page 12 of 1200

REJ09B0344-0200

Classification

Symbol

I/O

Name

Function

DQMLL

Byte select

Selects bits D7 to D0 when SDRAM

is connected.

DQMLU

Byte select

Selects bits D15 to D8 when

SDRAM is connected.

RASL

RAS

Connected to the

RAS pin when

SDRAM is connected.

CASL

CAS

Connected to the

CAS pin when

SDRAM is connected.

CKE

CK enable

Connected to the CKE pin when

SDRAM is connected.

Bus control

REFOUT

Refresh request

Request signal for refresh execution.

DREQ3 to

DREQ0

DMA-transfer

request

Input pins to receive external

requests for DMA transfer.

DACK3 to

DACK0

DMA-transfer

request accept

Output pins for signals indicating

acceptance of external requests

from external devices.

Direct memory

access controller

(DMAC)

TEND1, TEND0 O

DMA-transfer end

output

Output pins for DMA transfer end.

TCLKA,

TCLKB,

TCLKC,

TCLKD

MTU2 timer clock

input

External clock input pins for the

timer.

TIOC0A,

TIOC0B,

TIOC0C,

TIOC0D

I/O

MTU2 input

capture/output

compare

(channel 0)

The TGRA_0 to TGRD_0 input

capture input/output compare

output/PWM output pins.

TIOC1A,

TIOC1B

I/O

MTU2 input

capture/output

compare

(channel 1)

The TGRA_1 and TGRB_1 input

capture input/output compare

output/PWM output pins.

Multi-function

timer pulse unit

2 (MTU2)

TIOC2A,

TIOC2B

I/O

MTU2 input

capture/output

compare

(channel 2)

The TGRA_2 and TGRB_2 input

capture input/output compare

output/PWM output pins.

TIOC3A,

TIOC3B,

TIOC3C,

TIOC3D

I/O

MTU2 input

capture/output

compare

(channel 3)

The TGRA_3 to TGRD_3 input

capture input/output compare

output/PWM output pins.

R5F72115D160FPV Datasheet(PDF) 36 Page - Renesas Technology Corp

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