R5F72115D160FPV datasheet(47/1228 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 May. 08, 2008 Page 23 of 1200

REJ09B0344-0200

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Delayed Branch Instructions

With the exception of some instructions, unconditional branch instructions, etc., are executed as

delayed branch instructions. With a delayed branch instruction, the branch is taken after execution

of the instruction immediately following the delayed branch instruction. This reduces disturbance

of the pipeline control when a branch is taken.

In a delayed branch, the actual branch operation occurs after execution of the slot instruction.

However, instruction execution such as register updating excluding the actual branch operation, is

performed in the order of delayed branch instruction

→ delay slot instruction. For example, even

though the contents of the register holding the branch destination address are changed in the delay

slot, the branch destination address remains as the register contents prior to the change.

Table 2.3

Delayed Branch Instructions

SH-2A CPU

Description

Example of Other CPU

BRA

TRGET

ADD

R1,R0

Executes the ADD before

branching to TRGET.

ADD.W

R1,R0

BRA

TRGET

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Unconditional Branch Instructions with No Delay Slot

The SH-2A additionally features unconditional branch instructions in which a delay slot

instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code

size.

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Multiply/Multiply-and-Accumulate Operations

16-bit

× 16-bit → 32-bit multiply operations are executed in one to two cycles. 16-bit × 16-bit +

64-bit

→ 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit ×

32-bit

→ 64-bit multiply and 32-bit × 32-bit + 64-bit → 64-bit multiply-and-accumulate

operations are executed in two to four cycles.

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T Bit

The T bit in the status register (SR) changes according to the result of the comparison. Whether a

conditional branch is taken or not taken depends upon the T bit condition (true/false). The number

of instructions that change the T bit is kept to a minimum to improve the processing speed.

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