R5F72115D160FPV datasheet(85/1228 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 May. 08, 2008 Page 61 of 1200

REJ09B0344-0200

Section 4 Clock Pulse Generator (CPG)

This LSI has a clock pulse generator (CPG) that generates an internal clock (I

φ), a peripheral clock

φ), a bus clock (Bφ), an MTU2S clock (Mφ), and an AD clock (Aφ). The CPG consists of a

crystal oscillator, PLL circuits, and divider circuits.

4.1

Features

• Clock operating modes

Either the internal crystal resonator or the input on the external clock-signal line can be

selected.

• Five clocks generated independently

An internal clock (I

φ) for the CPU, a peripheral clock (Pφ) for the peripheral modules, a bus

clock (B

φ = CK) for the external bus interface, an MTU2S clock (Mφ) for the MTU2S module,

and an AD clock (A

φ) for the ADC module can be generated independently.

• Frequency change function

Internal and peripheral clock frequencies can be changed independently using the PLL (phase

locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software

using frequency control register (FRQCR) settings.

• Power-down mode control

The clock can be stopped for sleep mode and software standby mode, and specific modules can

be stopped using the module standby function. For details on clock control in the power-down

modes, see section 23, Power-Down Modes.

Figure 4.1 shows a block diagram of the clock pulse generator.

R5F72115D160FPV Datasheet(PDF) 85 Page - Renesas Technology Corp