R5F72115D160FPV datasheet(19/1228 Pages) RENESAS

19 / 1228 page

Rev. 2.00 May. 08, 2008 Page xix of xxiv

REJ09B0344-0200

16.3.3 I

2C Bus Mode Register (ICMR)............................................................................ 734

16.3.4 I

2C Bus Interrupt Enable Register (ICIER) ........................................................... 736

16.3.5 I

2C Bus Status Register (ICSR)............................................................................. 738

16.3.6 Slave Address Register (SAR) .............................................................................. 741

16.3.7 I

2C Bus Transmit Data Register (ICDRT)............................................................. 741

16.3.8 I

2C Bus Receive Data Register (ICDRR).............................................................. 742

16.3.9 I

2C Bus Shift Register (ICDRS)............................................................................ 742

16.3.10 NF2CYC Register (NF2CYC) .............................................................................. 743

16.4

Operation ........................................................................................................................... 744

16.4.1 I

2C Bus Format...................................................................................................... 744

16.4.2 Master Transmit Operation ................................................................................... 745

16.4.3 Master Receive Operation..................................................................................... 747

16.4.4 Slave Transmit Operation ..................................................................................... 749

16.4.5 Slave Receive Operation....................................................................................... 752

16.4.6 Clocked Synchronous Serial Format..................................................................... 754

16.4.7 Noise Filter ........................................................................................................... 758

16.4.8 Example of Use..................................................................................................... 759

16.5

Interrupt Requests .............................................................................................................. 763

16.6

Bit Synchronous Circuit..................................................................................................... 764

16.7

Usage Notes ....................................................................................................................... 767

16.7.1 Note on Multiple Master Usage ............................................................................ 767

16.7.2 Note on Master Receive Mode.............................................................................. 767

16.7.3 Note on Master Receive Mode with ACKBT Setting........................................... 767

16.7.4 Note on MST and TRS Bit Status When an Arbitration was Lost........................ 767

Section 17 A/D Converter (ADC)........................................................................769

17.1

Features .............................................................................................................................. 769

17.2

Input/Output Pins ............................................................................................................... 771

17.3

Register Descriptions ......................................................................................................... 772

17.3.1 A/D Control Register (ADCR) ............................................................................. 773

17.3.2 A/D Status Register (ADSR) ................................................................................ 776

17.3.3 A/D Start Trigger Select Register (ADSTRGR) ................................................... 777

17.3.4 A/D Analog Input Channel Select Register (ADANSR) ...................................... 779

17.3.5 A/D Data Registers 0 to 7 (ADDR0 to ADDR7) .................................................. 780

17.4

Operation ........................................................................................................................... 781

17.4.1 Single-Cycle Scan Mode....................................................................................... 781

17.4.2 Continuous Scan Mode ......................................................................................... 783

17.4.3 Input Sampling and A/D Conversion Time .......................................................... 785

17.4.4 A/D Converter Activation by MTU2 and MTU2S ............................................... 787

17.4.5 External Trigger Input Timing.............................................................................. 788

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