R5F72115D160FPV datasheet(15/1228 Pages) RENESAS

15 / 1228 page

Rev. 2.00 May. 08, 2008 Page xv of xxiv

REJ09B0344-0200

10.3.27 Timer Cycle Buffer Register (TCBR)................................................................... 431

10.3.28 Timer Interrupt Skipping Set Register (TITCR) ................................................... 431

10.3.29 Timer Interrupt Skipping Counter (TITCNT)....................................................... 433

10.3.30 Timer Buffer Transfer Set Register (TBTER) ...................................................... 434

10.3.31 Timer Dead Time Enable Register (TDER).......................................................... 436

10.3.32 Timer Waveform Control Register (TWCR) ........................................................ 437

10.3.33 Bus Master Interface ............................................................................................. 439

10.4

Operation ........................................................................................................................... 440

10.4.1 Basic Functions..................................................................................................... 440

10.4.2 Synchronous Operation......................................................................................... 446

10.4.3 Buffer Operation ................................................................................................... 448

10.4.4 Cascaded Operation .............................................................................................. 452

10.4.5 PWM Modes ......................................................................................................... 457

10.4.6 Phase Counting Mode ........................................................................................... 462

10.4.7 Reset-Synchronized PWM Mode.......................................................................... 469

10.4.8 Complementary PWM Mode ................................................................................ 472

10.4.9 A/D Converter Start Request Delaying Function.................................................. 518

10.4.10 MTU2–MTU2S Synchronous Operation.............................................................. 522

10.4.11 External Pulse Width Measurement...................................................................... 528

10.4.12 Dead Time Compensation..................................................................................... 529

10.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 532

10.5

Interrupt Sources................................................................................................................ 533

10.5.1 Interrupt Sources and Priorities............................................................................. 533

10.5.2 DMAC Activation................................................................................................. 535

10.5.3 A/D Converter Activation..................................................................................... 536

10.6

Operation Timing............................................................................................................... 538

10.6.1 Input/Output Timing ............................................................................................. 538

10.6.2 Interrupt Signal Timing......................................................................................... 545

10.7

Usage Notes ....................................................................................................................... 550

10.7.1 Module Standby Mode Setting ............................................................................. 550

10.7.2 Input Clock Restrictions ....................................................................................... 550

10.7.3 Caution on Period Setting ..................................................................................... 551

10.7.4 Contention between TCNT Write and Clear Operations...................................... 551

10.7.5 Contention between TCNT Write and Increment Operations............................... 552

10.7.6 Contention between TGR Write and Compare Match .......................................... 553

10.7.7 Contention between Buffer Register Write and Compare Match ......................... 554

10.7.8 Contention between Buffer Register Write and TCNT Clear ............................... 555

10.7.9 Contention between TGR Read and Input Capture............................................... 556

10.7.10 Contention between TGR Write and Input Capture.............................................. 557

10.7.11 Contention between Buffer Register Write and Input Capture ............................. 558

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