R5F72115D160FPV datasheet(77/1228 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 May. 08, 2008 Page 53 of 1200

REJ09B0344-0200

Compatibility

Instruction

Instruction Code

Operation

Execu-

tion

Cycles T Bit

SH2,

SH2E SH4 SH-2A

BXOR.B

#imm3,@(disp12,Rn)

0011nnnn0iii1001

0110dddddddddddd

(imm of (disp + Rn)) ^ T

→ T

Ope-

ration

result

Yes

2.5

Processing States

The CPU has five processing states: reset, exception handling, bus-released, program execution,

and power-down. Figure 2.6 shows the transitions between the states.

Power-on reset from any state

Manual reset from any state

Power-on reset state

Manual reset state

Program execution state

Bus-released state

Sleep mode

Software standby mode

Exception

handling state

Exception

handling

source

occurs

Exception

handling

ends

Bus request

generated

Bus request

cleared

STBY bit set

for SLEEP

instruction

NMI interrupt or

IRQ interrupt occurs

Power-down state

Reset canceled

STBY bit cleared

for SLEEP

instruction

Reset state

Bus request

cleared

Bus request

cleared

Bus request

generated

Bus request

generated

Interrupt source or

DMA address error occurs

Figure 2.6 Transitions between Processing States

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