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R5F72115D160FPV Datasheet(PDF) 91 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 91 Page - Renesas Technology Corp

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Section 4 Clock Pulse Generator (CPG)
Rev. 2.00 May. 08, 2008 Page 67 of 1200
REJ09B0344-0200
Table 4.3
Relationship between Clock Operating Mode and Frequency Range
PLL Frequency
Multiplier
Selectable Frequency Range (MHz)
Clock
Operating
Mode
FRQCR
Setting
PLL
Circuit 1
PLL
Circuit 2
Ratio of
Internal Clock
Frequencies
(I:B:P)*
1
Input Clock*
2
Output Clock
(CK Pin)
Internal Clock
(I
φ)
Bus Clock
(B
φ)
Peripheral
Clock (P
φ)
H'1000
On (
× 1)
On (
×4)
4:4:4
8 to 10
32 to 40
32 to 40
32 to 40
32 to 40
H'1001
On (
× 1)
On (
×4)
4:4:2
8 to 10
32 to 40
32 to 40
32 to 40
16 to 20
H'1003
On (
× 1)
On (
×4)
4:4:1
8 to 10
32 to 40
32 to 40
32 to 40
8 to 10
H'1005
On (
× 1)
On (
×4)
4:4:1/2
8 to 10
32 to 40
32 to 40
32 to 40
4 to 5
H'1101
On (
× 2)
On (
×4)
8:4:4
8 to 10
32 to 40
64 to 80
32 to 40
32 to 40
H'1103
On (
× 2)
On (
×4)
8:4:2
8 to 10
32 to 40
64 to 80
32 to 40
16 to 20
H'1105
On (
× 2)
On (
×4)
8:4:1
8 to 10
32 to 40
64 to 80
32 to 40
8 to 10
H'1111
On (
× 2)
On (
×4)
4:4:4
8 to 10
32 to 40
32 to 40
32 to 40
32 to 40
H'1113
On (
× 2)
On (
×4)
4:4:2
8 to 10
32 to 40
32 to 40
32 to 40
16 to 20
H'1115
On (
× 2)
On (
×4)
4:4:1
8 to 10
32 to 40
32 to 40
32 to 40
8 to 10
H'1303
On (
× 4)
On (
×4)
16:4:4
8 to 10
32 to 40
128 to 160
32 to 40
32 to 40
H'1305
On (
× 4)
On (
×4)
16:4:2
8 to 10
32 to 40
128 to 160
32 to 40
16 to 20
H'1313
On (
× 4)
On (
×4)
8:4:4
8 to 10
32 to 40
64 to 80
32 to 40
32 to 40
H'1315
On (
× 4)
On (
×4)
8:4:2
8 to 10
32 to 40
64 to 80
32 to 40
16 to 20
6
H'1333
On (
× 4)
On (
×4)
4:4:4
8 to 10
32 to 40
32 to 40
32 to 40
32 to 40
H'1335
On (
× 4)
On (
×4)
4:4:2
8 to 10
32 to 40
32 to 40
32 to 40
16 to 20
Notes:
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
2. The frequency of the clock input from the EXTAL pin or the frequency of the crystal resonator.
Caution:
1. The frequency of the internal clock (I
φ) is the frequency of the signal input to the CK pin after
multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Set
the frequency of the internal clock to 160 MHz or less but not less than the frequency of the
signal on the CK pin.
2. The frequency of the peripheral clock (P
φ) is the frequency of the signal input to the CK pin after
multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Set
the frequency of the peripheral clock to 40 MHz or less. In addition, do not set a higher
frequency for the internal clock than the frequency on the CK pin.
3. The frequency multiplier of PLL circuit 1 can be selected as
×1, ×2, or ×4. The divisor of the
divider can be selected as
×1, ×1/2, ×1/4, or ×1/8. The settings are made in the frequency-
control register (FRQCR).
4. The signal output by PLL circuit 1 is the signal on the CK pin multiplied by the frequency
multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL circuit 1 is no more
than 160 MHz.



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